Metallurgical Cross Sectioning of Microelectronic   Packages for Optical Inspection and Electron Beam Analysis(1)

Robert James Burgoyne
Analog Devices, Inc.

Abstract

Advanced integrated circuit packaging technologies present the analyst with a wide range of packaging materials and geometries. Successful cross sectioning of these devices yields critical construction and/or defect information not obtainable from any other analytical method. This paper will address the practice of producing deformation-free encapsulated cross sections for use in package and process development, failure analysis and materials characterization. Sample preparation sequences for plastic, metal and ceramic packages will be reviewed, along with the results obtained during Scanning Electron Microscope (SEM) and Energy Dispersive Spectroscopy (EDS) analysis of the sections.

METALLOGRAPHIC CROSS SECTIONING of microelectronic packages is a valuable analytical procedure widely used within the semiconductor industry. It is used for a variety of reasons, including package qualification, monitoring of the manufacturing process, incoming quality control and failure analysis. Proper implementation yields results that are unambiguous and can be used as either a sole source of information or to validate data gathered from previously performed, non-destructive analytical procedures. Until recently, cross sectioning of microelectronic components and packages was performed using techniques similar to those used in the metallurgical industry. That is, the sectioned mounts were subjected to successively finer fixed abrasives for the grinding process, and polished to the final finish using an aluminum oxide or similar slurry dispensed onto a low to medium napped cloth. While this method may have been acceptable in the past, subjecting today's state-of-the-art microelectronic packages to this type of sample preparation is ineffective and in some cases results in catastrophic damage. This paper details the practical aspects of producing deformation-free encapsulated cross sections of microelectronic packages using readily available consumable items and semi-automatic sample preparation equipment. The resulting cross sections are suitable for optical inspection, dimensional measurements and a variety of electron beam imaging and analytical techniques.

Figure 1 (see appendix) illustrates a typical flow for conducting metallurgical cross sectioning. Certain steps can often be omitted if the cross section is in support of a routinely performed process monitor where established procedures are to be used for the analysis

Figure 1 (Typical Sample Preparation Flow Chart)

Discussion

Package Characteristics. Before plunging into specimen preparation, it is essential to have a general understanding of the physical properties of all materials used in the construction of the package. Table 1 details the diverse properties of the materials that are found within a typical ceramic sidebraze package.

Table 1

As can be seen, the industry standard ceramic sidebraze package shown above contains a significant number of highly dissimilar materials. Further advances in microelectronic packaging technologies has substantially increased the complexity of these packages. Ordinarily, the preparation sequence selected is tailored to the predominant component material or the primary component material(s) to be analyzed. However, the analyst must consider all component materials when selecting or developing a sample preparation sequence for this sample class. Ignoring the unique interfaces that are present in a microelectronic package will likely result in preparation induced artifacts. Microelectronic packages are particularly prone to artifacts such as edge rounding, relief, embedding, smearing and fracturing. (Sample preparation artifacts and recommended corrective actions will be discussed at the end of this paper for easy reference.) Preparation induced artifacts could be misinterpreted as flaws in the manufacturing process.

Supplemental Analysis. Metallurgical cross sectioning is a destructive test. As such, it is important to gather as much information as possible about the device to be sectioned prior to the encapsulation process. Doing this will furnish the analyst with a record to fall back on should questions arise such as whether a defect was pre-existing or induced during the preparation sequence.

Devices submitted for routine process monitors (e.g. measuring die attach thickness, plating thickness, etc.) require little or no preliminary analysis. Nonetheless, since many section requests are in support of a failure analysis where a specific defect is of interest, supplemental analysis is often required.

In order to better understand the package architecture and to successfully section through a specific plane of interest, a number of supplementary analysis techniques should be considered prior to encapsulation. These include, but are not limited to, radiography, ultrasonic imaging, fine and gross leak testing, die penetration and macro photography. A detailed discussion of these techniques is not pertinent to this paper and therefore will not be included.

Figure 2 illustrates the results obtained during radiographic inspection of a plastic multi-chip module that will be sectioned for this paper. Note the double sided circuit board substrate, printed interconnects, thru-holes, and bonding wires.

Figure 2

Sample Considerations. Cleanliness is one of the most important factors in a cross sectioning environment. A clean, well organized and ergonomic laboratory will not only increase efficiency, but eliminate the potential for cross contamination when dealing with the many different preparation abrasives.

Although a clean working environment is important, package cleanliness is paramount. A properly cleaned package is critical in obtaining a tight bond between the mounting resin and all external package surfaces. Conversely, a package contaminated with identification labels, pencil or felt tip marker residue, finger oils or other hydrocarbons will usually lead to poor adhesion and, ultimately, package to resin delamination.

Cleaning is best accomplished by putting the package in a beaker filled with acetone, and then placing the beaker in an ultrasonic tank that is operated for several minutes. (Of course, the cleaning technique best suited for your application may vary. Some materials may be adversely effected by either acetone or ultrasonic exposure. It is always best to consult with the package vendor or other cognizant source before selecting a cleaning agent.) The high frequency cavitation produced by the sonic cleaner ensures that surface foreign material is removed from tight spaces. All handling of the package from this point forward should be done with a clean pair of stainless steel or plastic tweezers to prevent re-contamination. After removing the package from the beaker, immediately dry it with a blast of N2 gas or microscopically pure air. The use of compressed air from a facilities system is not recommended for sample drying. Hydrocarbons from the compressor oil and/or contamination from piping lines are always present and would be deposited onto the package during such a drying process. Placing the package in a low temperature (~50°C) vacuum bake-out oven for approximately 10 minutes is recommended for extracting any adsorbed residual moisture from the pores of the packaging material.

Encapsulation. The first part of the encapsulation process is to position the package in the sample cup such that the plane of interest will ultimately be parallel to the cutting blade. More often than not, it is necessary to support the package. This is typically accomplished by using plastic "spring" clips, double sided adhesive tape or PSA backed cardboard. If plastic clips are used for support, they must be cleaned in the same manner as with the package.

Microelectronic packages are fragile and cannot withstand the tremendous heat and pressure associated with compression molding. For this reason, cold mounting materials are used for the encapsulation process. Figure 3 provides a simple comparison of the three most commonly used cold mounting materials and their relevant properties.

Figure 3

For microelectronic applications, epoxies offer the best overall performance. Moderate heat generation during polymerization results in minimum shrinkage, while at the same time providing the high level of hardness necessary for proper edge retention. The only drawback to epoxies is the lengthy cure time; however, this time is generally a small fraction of the overall time required to complete an analysis.

The use of a vacuum impregnation chamber and a pressurization vessel are highly recommended when casting microelectronic packages. Vacuum impregnation is a process in which both the sample cup and resin mixture are placed in a chamber and evacuated using a stand alone vacuum pump. The vacuum removes entrapped air from the pores and other small topographical features of the package, making it possible for the resin to impregnate and consolidate the whole structure. (For best results, cast only enough resin to cover the package, if applicable, and then slowly return the chamber to atmospheric pressure. Although short in duration, the back pressure will further the penetration of resin into the confined areas of the package. Repeat the process and completely fill the sample cup.) Optimum resin penetration is achieved when the sample cup is placed in a pressure vessel and subjected to 40 psi of pressure for a minimum of five minutes.

For most metallurgical applications, satisfactory results can be obtained by using either a vacuum impregnation system or a pressurization system. However, microelectronic packages are one of the few classes of samples that benefit from using both systems. Although the vacuum impregnation system satisfactorily removes entrapped air from the sample, surface tension often prevents the resin from filling extremely small topographical features, such as those on the surface of an integrated circuit. The benefit of the pressurization system is that the pressure helps overcome the surface tension factor and forces the resin into these tight areas.

Figure 4 shows the surface of an integrated circuit after sample preparation. The package was vacuum impregnated using epoxy resin and then placed in a pressure vessel at 40 psi for five minutes. Note that the resin conforms to the topography of the integrated circuit. Furthermore, note the minimal shrinkage observed at the passivation to epoxy interface. The sample was imaged in a SEM in BSE mode (atomic number contrast) at 2,200X magnification.

Figure 4

Sectioning. One might think that the sectioning process is the "easiest" part of the sample preparation sequence; simply place the mount in a holding fixture, attach it to the saw, and begin sectioning. However, proper sectioning is critical in that it establishes the baseline for the rest of the sample preparation process. The sectioning process will always induce some level of deformation; however, with a thorough understanding of the parameters that affect sectioning, initial damage can be minimized and the time spent on subsequent preparation steps will be significantly reduced. Conversely, a haphazard approach to sectioning could create initial deformation that is irreversible.

Table 2 provides a quick reference of the sectioning parameters of concern and the optimum settings for sectioning microelectronic packages.

Table 2

Direction of cut and sample orientation are also key factors when sectioning microelectronic packages. As a general rule, it is best to orient the sample, with respect to blade rotation, such that the brittle material is cut in compression. Doing this will minimize delamination and/or fracturing of the brittle component material. (Experience has shown that it is always best to section microelectronic packages with the silicon chip in compression, even in the case of brittle ceramic substrates. This is critical when packages are sectioned prior to encapsulation; however, it is a good practice to follow this rule even when sectioning encapsulated packages.) Furthermore, the mount should be positioned such that the smallest dimension of the package is parallel to the saw blade. This will result in faster cutting of the sample without a sacrifice in the quality of the section.

Figure 5 illustrates the least and most desirable orientations of the mount with respect to a brittle component and the smallest package dimension.

Figure 5

Figure 6 shows an "as cut" ceramic dual-in-line package (lid removed) that was sectioned using the criteria established in Table 2. Note the "crisp" interfaces that exist between the silicon chip, silver filled epoxy die attach and ceramic substrate; the absence of fracturing or cracking of the silicon chip; and the lack of smearing of the soft silver filled epoxy die attach material. This "as cut" sample was imaged in a SEM in secondary electron mode at 50X magnification.

Tables 3 and 4 (see appendix) detail the preparation sequences for ceramic and metal alloy packages and plastic packages, respectively. These tables should be referenced when reading the following process descriptions.

Figure 6

Planar Grinding. The purpose of the planar grinding, or lapping, process is to: 1) remove the initial deformation induced during sectioning, 2) produce a uniform flatness across all component materials and 3) bring multiple mounts into a common polishing plane.

To begin the overall grinding sequence, sectioned mounts are loaded onto a carousel type sample holder so that several mounts can be prepared simultaneously. Before loading, however, bevel the sectioned end with #240 silicon carbide (SiC) paper, taking care not to grind into the edge of the package. After loading, gently color the sectioned area (that is, the area that will be ground) of each mount with a black indelible felt tipped marker. Doing this will make it easier to identify when all the mounts are at a common polishing plane.

Planar grinding of ceramic and metal alloy microelectronic packages is best accomplished using a 15?m water based, poly-crystalline diamond suspension applied onto a hard lapping plate. Since free abrasives are much less aggressive than fixed abrasives, the material removal rate will be lower. Planar grinding in this fashion usually takes about 10 - 15 minutes, considerably longer than the time required when fixed abrasives are used. This is an acceptable trade-off when considering the benefits of reduced deformation and a decrease in the likelihood of forming cracks. Lapping is also very effective at maintaining the flatness of packages containing highly dissimilar materials. The use of an abrasive greater than 15?m for planar grinding is not recommended. Even when applied onto a hard lapping plate, the larger abrasives cause considerable, and sometimes irreversible, damage to the silicon chip.

Samples containing predominately soft and ductile materials are prone to smearing, distortion and embedding of the rolling abrasives. Samples of this category are frequently planarized using a fixed abrasive technique. This is an acceptable approach when all the component materials are soft. However, if the plane of interest includes the silicon chip, or other brittle component, an advanced technique must be employed to prevent damage to the brittle component material. In this situation, a medium-hard lapping plate, with a 9?m oil based, poly-crystalline diamond suspension is used for planar grinding. Minimizing the abrasive size, plate speed and applied force per sample significantly reduces the likelihood of smearing and embedding, while at the same time maintaining sample flatness and the integrity of the brittle component. This advanced approach will take longer, sometimes up to 30 minutes; nonetheless, the benefits of rolling abrasives on lapping plates make it time well spent.

In both cases described above, the condition of the lapping surface is very important. A concave or convex surface profile will always result in an increase in grinding time. Conditioning (or dressing) plates is very straightforward and should be performed when planarization times begin to exceed normal or "as expected" limits for the given sample.

Planar grinding is a lengthy process. The frequent application of an extender fluid or additional diamond suspension is necessary to prevent "gumming" of the plate surface and to promote material removal. During planar grinding, the abrasives are free to go anywhere, including over the edge of the lapping plate and down the drain. Because of this loss of abrasives, it is best to repeatedly re-charge the lapping plate with diamond suspension instead of an extender fluid.

Sample Integrity. The goal of any sample preparation sequence is to remove all deformation induced from the previously performed preparation step. For metallurgical samples, the process usually involves the use of successively finer abrasives, followed by one or more final polishing steps. Microelectronic packages are more delicate and due to their highly diverse materials will not respond well to this methodology.

Sample integrity is the process in which all deformation incurred during planar grinding is removed, thus revealing, for the first time, the true microstructural characteristics of the materials being prepared. The objective of this intermediate step is to satisfactorily remove all deformation created during planar grinding, while at the same time imparting no further deformation. Further, the sequence selected must be capable of maintaining the flatness obtained during planar grinding.

There are several different ways to approach the sample integrity phase of preparation. This is largely due to the wide variety of consumable items that are available to the analyst. As an example, assume that the sample being prepared is a ceramic sidebraze package. Following planar grinding, the analyst could elect to continue power lapping, in which case a medium-hard lapping surface with a 6µm water based poly-crystalline diamond suspension would be utilized. Another option is to use napless, chemotextile products. These products are excellent for use in the intermediate stages of microelectronic sample preparation because they cut aggressively, yet are capable of maintaining the desired flatness of the sample. In either situation, the analyst may choose to add alkaline colloidal silica along with the diamond suspension, thus adding the element of mechanochemical material removal to the process. The sample integrity phase can sometimes be accomplished in one step; however, two steps are often needed to avoid abrupt transitions in abrasive sizes. All sectioned packages described in this paper were subjected to a two step process. Similarities include the use of chemotextile cloths with colloidal silica applied to support mechanochemical material removal. Differences include the abrasives used (6µm/1µm for predominantly hard packages versus 3?m/1?m for predominately soft packages) and, when working with predominately softer materials, a decrease in applied pressure and wheel speed.

When in doubt, or when developing a new procedure, select consumable items that will, as a minimum, maintain a uniform flatness across the sample. In this way, if the first effort fails to yield adequate results, at least the sample will be in an acceptable condition for a second try without having to repeat the planar grinding process.

Final Polish. Once the intermediate stage of sample preparation is completed, the true microstructure of the sample is clearly visible. However, fine abrasive scratches and/or smearing of soft, ductile components are still apparent and must be removed before the surface is considered free from mechanically induced deformation. The goal of final polishing is to do just that: remove all residual deformation from the sample without inducing any artifacts.

Final polishing utilizes submicron abrasives that remove only the slightest amount of material. As such, this final step cannot correct for gross artifacts (i.e. relief, edge rounding, fracturing, etc.) induced during previously performed preparation steps. Attempts to use final polishing to correct for such preparation errors will do nothing more than waste time and expensive consumable items. For the most part, microelectronic packages fall into one of two main categories: predominately hard materials (e.g. ceramic based and metal alloy based) or predominately soft materials (e.g. plastics). As a general rule, hard materials are polished using hard, napless chemotextile cloths and soft materials are polished using low to medium napped cloths. At times, however, it may be necessary to use two final polishing steps. Take, for example, the complex construction of the ceramic sidebraze package detailed in Table 1. In this situation, the first final polish step would concentrate on the hard brittle components. This can often lead to smearing of the softer component materials. A second step would then be needed to polish the softer materials.

With regards to abrasives, hard materials polish very well with straight colloidal silica suspension. Increasing both the speed of the wheel and the applied pressure helps further mechanochemical material removal. Conversely, softer materials polish well using a homogenous mixture of 50% colloidal silica and 50% deagglomerated alumina (0.05µm). Here, time and pressure must be kept to a minimum to reduce the likelihood of generating edge rounding and microstructural relief artifacts.

Vibratory Polishing. In most cases, sample preparation is concluded after the final polishing stage. However, to achieve the ultimate in polish quality, one additional step, vibratory polishing, is required. Vibratory polishers facilitate single or multiple samples and are the least aggressive with respect to material removal. As such, it is not uncommon for this supplementary step to take up to several hours, or even overnight, to complete. (The length of time is dependent upon the quality of the sample after final polishing and the objective of the section itself.) Because of the time involved, it is best to use a low nap or napless cloth with either straight colloidal silica suspension, submicron alumina or a homogeneous mixture of both. (Cloths with a medium or high nap are not recommended. The selective eroding action inherent with these cloths, coupled with long polishing times, will lead to edge rounding and microstructural relief.) Straight colloidal silica works well on both hard and soft materials and, due to the high pH of the aqueous base, will produce a slight etch artifact on most microelectronic package constituents.

Etching. Etching is a broad topic, one that is subject to manufacturer's specifications; the objective of the cross section; preference of the analyst; the methodology employed; and the complexity of the sample. For the purpose of this paper, one specific technique, plasma field delineation, will be discussed.

Plasma systems have long been used by the semiconductor industry for various wafer fabrication processes. Benchtop versions typically found in failure analysis or reliability laboratories can be used for delineation of microelectronic package cross sections. Their ability to provide uniform anisotropic etching makes them ideal for such tasks.

Several gases are available for use in the selective delineation of the deposited layers found on an integrated circuit. These include, but are not limited to, sulfur-hexafluoride (SF6), trifluoromethane (CHF3) and DE-101, a mixture of He, O2 and carbon-tetrafluoride (CF4).

Figure 7 shows the deposited layers of the integrated circuit following a three minute sulfur-hexafluoride (SF6) plasma etch. Note the clean interfaces between the various deposited layers as well as the trench isolation details. This sample was imaged in a SEM, in secondary electron mode, at 2,500X magnification.

Figure 7

Oxygen plasma has recently emerged as a means of cleaning organic residue from microelectronic devices following the assembly process. Oxygen plasma can also be used for etching microelectronic packaging materials containing organic elements.

Figure 8 shows the dramatic results obtained when the plastic multi-chip module sectioned for this paper was subjected to an oxygen plasma field for five minutes. Note the relief etch effects observed within the printed circuit substrate, silver filled epoxy die attach and the bulk plastic of the package. The sample was imaged in a SEM, in secondary electron mode, at 500X magnification and 50° tilt.

Figure 8

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